Comtech EF Data Vipersat CDD-564L Specifikace stáhnout pdf (Strana 29)

CDD-562L/564 Demodulator with IP Module Revision 1

Introduction MN/CDD564L.IOM

1–3

The demodulator signal processing functions are performed in two, large Field-Programmable Gate

Array (FPGA), which permits rapid implementation of changes, additions and enhancements in the

field. These signal-processing functions are controlled and monitored by a 32-bit RISC

microprocessor, which also controls all front panel indicators, serial and Ethernet interfaces.

As shown in the block diagrams depicted in Figure 1-3, t

he demodulator is physically comprised

of a single printed circuit board assembly, with integral Turbo FEC and IP router.

CDD-562L Block Diagram

CDD-564/564L Block Diagram

Figure 1-3. CDD-5xx Block Diagrams

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 171 172

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Comtech EF Data Vipersat CDD-564L Specifikace Strana 29